1. Field of the Invention
The present invention relates to a test apparatus.
2. Description of the Related Art
A voltage margin test is performed on a semiconductor device, which is a device under test, that includes a high-speed transmission interface. The voltage margin test is a test in which such a device under test (DUT) is tested so as to determine whether or not it has a sufficient margin for fluctuation in the input signal voltage level. For example, a signal input to the semiconductor device including a binary interface can be set to two voltage levels, i.e., high level VH and low level VL. Upper limit values (VHmax, VLmax) are set for the respective two voltage levels, and lower limit values (VHmin, VLmin) are also set for the respective two voltage levels. Alternatively, an upper limit value Amax and a lower limit value Amin are set for the amplitude of the signal. In the voltage margin test, such a DUT is tested to determine whether or not it has an allowable margin ranging from the lower limit value VHmin up to the upper limit value VHmax with respect to fluctuation in the high level of the input signal, and whether or not it has an allowable margin ranging from the lower limit value VLmin up to the upper limit value VLmax with respect to fluctuation in the low level of the input signal. Alternatively, the DUT is tested to determine whether or not it has a margin ranging from the lower limit value Amin up to the upper limit value Amax with respect to fluctuation in the amplitude of the input signal. FIG. 1 is a graph showing an allowable voltage margin of such a binary interface.
With typical arrangements employing a binary signal, when the voltage level of the input signal is close to a voltage level (reference level) Vref on the basis of which the binary logical judgment is made, i.e., when the amplitude of the input signal is small, bit error is likely to occur. In order to solve such a problem, with conventional test apparatuses, a voltage margin test is performed using a test pattern signal having a voltage level combination (VHmin, VLmax) which produces the minimum amplitude.